Bonded wafers are used as wafers for high performance devices. Each of the bonded wafers is manufactured by bonding a semiconductor wafer with another wafer or the like and then thinning the wafer on the side where devices are fabricated.
Specifically, for example, two mirror-polished silicon wafers are prepared, and an oxide film is formed at least on one of the wafers. Then these wafers are brought into close contact to each other and subjected to a heat treatment at a temperature of from 200 to 1200° C. to increase bonding strength. After that, the wafer on the side where devices are fabricated (a bond wafer) is ground, polished and the like to thin the wafer so that the bond wafer has a desired thickness. As a result, a bonded SOI wafer comprising an SOI (Silicon On Insulator) layer can be manufactured.
It should be noted that the bonded wafer can be manufactured by directly bonding silicon wafers together without interposing an oxide film therebetween. Furthermore, as the base wafer, an insulator wafer made of quartz, silicon carbide, alumina, or the like can be used.
When the bonded wafer is manufactured as mentioned above, each of two mirror-surface wafers to be bonded has a portion referred to as a polishing sag, which has a slightly thinner thickness on the periphery, and a chamfered portion. Such portions are not bonded or left as unbonded portions having weak bonding strengths. When the bond wafer is thinned by grinding or the like in the presence of such unbonded portions, the unbonded portions delaminate in part in the thinning step. Therefore, the thinned bond wafer has a smaller diameter than the wafer to be a base (a base wafer). The bond wafer also has micro unevenness continuously formed in the periphery.
When such a bonded wafer is subjected to a device process, remaining unbonded portions delaminate in the device process. This generates particles and deteriorates device yield.
In order to overcome the problems, there is proposed a method of removing the remained unbonded portions beforehand by alkaline etching using KOH, NaOH, or the like (see Japanese Patent Application Laid-open (kokai) No. 10-209093). In alkaline etching, the etching rate of an etchant against Si (RSi) is fast, whereas the etching rate of the etchant against SiO2 (RSiO2) is slow. Therefore, the selectivity ratio (RSi/RSiO2) between the etching rates is large. In this case, on reaching a buried oxide film, etching from the bond wafer side automatically almost stops. In this way, use of alkaline etching is advantageous in that a buried oxide film is utilized as a protective film for protecting a base wafer from etching.